For our principal partners we offer deep insights and relationships into the semiconductor industry and can help grow your product portfolio, provide you valuable insight into the market and perform business development function for our clients.


Our Partners


ICScape - tools to accelerate SOC design closure

  • Clock Explorer - clock constraints clean up and analysis works in conjunction with CTS tool that improves CTS QoR, reduces clock insertion delay for faster timing closure, and significantly lowers clock tree power
  • QuaLib - IP and SOC block LINTing for layout, LEF, .lib and verilog models.  Checks integrity and consistency of models
  • Skipper Chip Finishing Platform - highest capacity can handle over 100GB GDS with layout editing, net tracing, Boolean operations.  Fastest layout comparisons, DRC/LVS debugging, and cell swapping and IP merging.


OmniPhy is a leading provider of differentiated interface IP, offering customers greater design margins and fast time-to-market for emerging standards, including 15-28Gb/s PHY designs. The company focuses on power and performance, yield, and testability - offering best-in-class silicon-proven IP in the most advanced technologies.  

OmniPhy provides PHY and SERDES IP for several consumer and networking protocols including PCIe, USB, HDMI, MHL, DDR, LPDDR, and 25/28G SERDES.

S3 Group

Leaders in mixed signal and analog IP.  S3 Group has an extensive portfolio of over 260+ RF and mixed signal cores including Power Management, ADC, DACs, Analog Front Ends, RF and Microwave cores.  S3 Group’s focus in wireless and wireline communications, Digital Broadcasting, Imaging, and Industrial markets.


Semifore automates and validates firmware RTL register automation supporting the SW/HW architectural requirements.  CSRCompiler reads and writes IP-XACT, SystemRDL and spreadsheets and with over 1,000 semantic and syntax checks that capture proper register behavior in an automated platform.  CSRCompiler is a universal translator from architectural representations to automated RTL, UVM test bench, firmware c_header files and documentation.  All at the fraction of the cost of home grown solutions.

  • Teklatech - resolves the challenges of next generation technologies that 16nm, 10nm and 7nm place on timing closure and die size.  Using Teklatech saves valuable routing resources thereby enabling your current design tools (Synopsys ICC and Cadence Innovus) to close timing that much faster or shrink your die size.  Please contact us for more information on Teklatech.

True Circuits  
True Circuits

True Circuits develops and markets a broad range of Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), and other mixed-signal designs for integrated circuits for the semiconductor, systems and electronics industries.

  • UltraSOC - suite of IP for silicon debug, performance monitoring, optimization and analytics.  It is non-intrusive, and runs at wire speed.   UltraSOCs portfolio IP supports all major CPUs including ARM, MIPS, Tensilica, CEVA and ARC, protocol-aware probes for buses, memory interfaces and custom logic monitors.  Significantly reduces silicon bring-up and debug time and reduces time to market. 

Verifyter was founded early 2010 with the mission to transform the development process by automating the diagnosis of software and hardware failures. Until now, diagnosis has been performed manually, keeping scores of engineers busy in the development organizations and preventing them from taking on new and more interesting challenges. Verifyter is dedicated to free the engineers from this chore to let them focus on the bigger picture.